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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. high-efficiency pwm led driver with boost converter and five constant-current gpio ports max6948b general description the max6948b general-purpose input/output (gpio) peripheral drives a series string of white leds (wleds), and contains up to five general-purpose input/output (gpio) ports to drive additional leds. the integrated 2mhz boost converter minimizes the size and cost of external components and supplies 30ma of load current at up to 28v. the converter is stable under all load conditions from 5v up to 28v and includes open-circuit detection to prevent damage to the ic. an i 2 c-programmable 10-bit pulse-width modulation (pwm) signal enables 1024 levels of wled intensity. the five gpio ports function as logic inputs, open- drain logic outputs, or constant-current sinks in any combination. ports withstand 5.5v independent of the max6948bs supply voltage. two of the ports drive addi - tional leds up to 30ma/port, while the other three ports drive leds at up to 10ma/port. the max6948b features shutdown and standby modes for low-power dissipa - tion. the constant-current drivers contain programmable pwm outputs and allow staggering to reduce the input peak-current requirements. the i/o ports also feature ramp-up and ramp-down controls. the max6948b features a single input to select from four i 2 c slave addresses. programming and functionality for the five gpio ports is identical to the max6946/max6947 i/o expanders. the max6948b is available in a 25-bump (2.31mm x 2.31mm) wlp package for cell phones, pdas, and other portable consumer electronic applications. the max6948b operates over the -40 n c to +105 n c tempera - ture range. applications led backlighting for lcds cell phones pdas handheld games portable consumer electronics features s 28v step-up dc-dc converter with integrated nmos power switch s built-in 10-bit pwm control for improved efficiency s no discharge path during pwm off period for increased battery life s fixed 2mhz switching for smaller components drives up to 6 series wleds s 8kv human body model (hbm) esd protection for gpios and boost-converter output s five open-drain gpios capable of constant- current led drive with individual 8-bit pwm intensity control s 2.7v to 5v power-supply operation s 400kbps, 5.5v tolerant i 2 c interface s four i 2 c slave address choices s rst input clears serial interface and exits shutdown (reset-run option) s small (2.31mm x 2.31mm) wlp package 19-4935; rev 0; 9/09 ordering information + denotes a lead(pb)-free/rohs-compliant package. typical operating circuit evaluation kit available note: r b = 0.2v/i led = 0.2v/0.03a = 6.7i. 2.7v to 5.0v 1.7v to v+ lx v+ scl sda rst scl sda rst v dd comp ad0 gnd out pgnd fb ledsw b g r p0 p1 p2 p3 p4 0.22ff r b 10h 0.1ff 47nf v ext max6948b 2.2ff part temp range pin-package MAX6948BGWA+ -40 n c to +105 n c 25 wlp
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 2 max6948b v+ to gnd ............................................................... -0.3v to +6v v dd , comp to gnd .................................... -0.3v to (v+ + 0.3v) pgnd to gnd ...................................................... -0.3v to +0.3v lx to pgnd (note 1) ............................................. -0.3v to +30v current into lx (note 1) ................................................... 700ma out, ledsw to pgnd (note 1) ........................... -0.3v to +30v p0Cp4 to gnd ......................................................... -0.3v to +6v rst , sda, scl, ad0 to gnd .................. -0.3v to (v dd + 0.3v) fb to pgnd (note 1) ............................................ -0.3v to +0.3v i.c. to gnd ........................................................... -0.3v to +0.3v dc current on p0Cp4 ......................................................... 50ma dc current on sda ............................................................ 10ma total gnd current ............................................................ 150ma total pgnd current ......................................................... 150ma continuous power dissipation (t a = +70 n c) 25-bump wlp (derate 10.8mw/ n c above +70 n c) ...... 866mw junction-to-ambient thermal resistance ( b ja ) (note 2) 25-bump wlp .............................................................. 93 n c/w operating temperature range (t min to t max ) .............................................. -40 n c to +105 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c esd protection human body model (r d = 1.5k i , c s = 100pf) p0Cp4, out, ledsw, fb to gnd ................................ q 8kv all other pins ................................................................ q 2kv lead temperature (soldering, 10s) 25-bump wlp ............................................................. (note 3) electrical characteristics ( typical application circuit , v+ = 2.7v to 5.0v, v dd = 1.7v to v+, t a = t min to t max , unless otherwise noted. typical values are at v+ = 3.3v, v dd = 2.5v, t a = +25 n c.) (note 4) absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: lx, fb, ledsw pins have an internal clamp diode to pgnd. applications that forward bias these diodes should take care not to exceed the power dissipation limits of the device. note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a single-layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal- tutorial . note 3: refer to the pb-free solder reflow requirement in j-std -020, rev d.1. parameter symbol conditions min typ max units operating supply voltage (v+) v+ 2.7 3.3 5.0 v operating supply voltage (v dd ) v dd 1.7 2.5 v+ v output load external supply voltage v out boost-converter output 28 v port external supply voltage v ext p0Cp4 at high impedance 5.5 v port voltage (p0, p4) v port constant-current on v+ v power-on-reset voltage v por voltage rising 1.7 v standby current i stby standby mode, boost converter off, rst = v dd , all digi - tal inputs at v dd or gnd t a = +25 n c 1.5 4 f a t a = t min to t max 6 standby current in reset (interface active) i rst standby mode, rst = gnd, f scl = 400khz, all other digital inputs at v dd or gnd t a = +25 n c 1.6 4 f a t a = t min to t max 6
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 3 max6948b electrical characteristics (continued) ( typical application circuit , v+ = 2.7v to 5.0v, v dd = 1.7v to v+, t a = t min to t max , unless otherwise noted. typical values are at v+ = 3.3v, v dd = 2.5v, t a = +25 n c.) (note 4) parameter symbol conditions min typ max units change in supply current per 30ma port d i dd30 one port set to 30ma constant cur - rent; all other ports are digital inputs at v dd or gnd t a = +25 n c 3 6.2 ma t a = t min to t max 7 change in supply current per 10ma port d i dd10 one port set to 5ma constant current half-current setting; all other ports are digital inputs at v dd or gnd t a = +25 n c 1.3 1.7 ma t a = t min to t max 2 gpio ports (p0Cp4) input high voltage v ih1 port i/o register value set to 0x01 (0.7 x v dd ) v input low voltage v il1 port i/o register value set to 0x01 (0.3 x v dd ) v input leakage current i in 0.03 q 1 f a input capacitance 10 pf 30ma port sink constant current (p0, p1) i port30 port i/o register value set to 0x02, v+ = 3.3v, v ext - v led = 0.5v to 1.5v (note 5) t a = +25 n c 27 30 34 ma t a = t min to t max 25 35 10ma port sink constant current (p2, p3, p4) i port10 5ma half-current setting, port i/o register value set to 0x02, v+ = 3.3v, v ext - v led = 0.5v to 1.5v (note 5) t a = +25 n c 4.4 5 5.6 ma t a = t min to t max 3.7 6.3 logic output low voltage v ol1 i sink = 2ma, port i/o register value set to 0x00 0.17 0.3 v 30ma port sink constant-current matching (p0, p1) d i port30 constant current set to 30ma, v+ = 3.3v, t a = +25 n c (note 6) v port = 1v q 0.7 q 5 % v port = 2.75v q 5 10ma port sink constant-current matching (p2, p3, p4) d i port10 constant current set to 5ma half-current setting, v+ = 3.3v, t a = +25 n c (note 6) v port = 1v q 2 q 5 % constant-current slew time 20% current to 80% current, port i/o regis - ter value changed from 0x01 to 0x02 2 f s
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 4 max6948b electrical characteristics (continued) ( typical application circuit , v+ = 2.7v to 5.0v, v dd = 1.7v to v+, t a = t min to t max , unless otherwise noted. typical values are at v+ = 3.3v, v dd = 2.5v, t a = +25 n c.) (note 4) parameter symbol conditions min typ max units boost converter undervoltage lockout threshold v uvlo v+ rising 2.65 v v+ falling 2.3 undervoltage lockout threshold hysteresis v hys 30 mv continuous output current i wled 100% boost led pwm, full-current setting, r b = 6.67 i , i wled = v fb /r b 30 ma operating current run bit = 1, boost standby bit = 0, 0% boost led pwm 2 ma lx current limit v+ = 3.3v, t a = +25c 430 500 570 ma lx saturation voltage i lx = 200ma 0.1 0.25 v lx leakage current i lxoff 0% boost led pwm, v lx = 10v 8 f a out leakage current i outoff v out = 28v, boost converter in shutdown 16 23 f a operating frequency f boost 2 mhz minimum duty cycle continuous conduction mode 10 % discontinuous conduction mode 0 maximum duty cycle 95 % gm amplifier transconductance 250 f s fb leakage current i fb v fb = 100mv 0.01 q 1 f a feedback output voltage v fb half-current setting, v+ = 3.3v, t a = +25c 94 100 106 mv full-current setting, v+ = 3.3v, t a = +25c 190 200 210 half-current setting 90 100 110 full-current setting 175 200 225 quick-start charge current i qs 150 f a quick-start time from enable command stop condition to output regulation, c comp = 0.047 f f (note 7) 3.5 5 ms shutdown discharge resistance r comp 20 k i output current line regulation 3.0v < v+ < 5.0v 2 %/v thermal shutdown threshold 150 n c thermal shutdown threshold hysteresis 9 n c overvoltage threshold v ov v out rising 28 29 30 v overvoltage threshold hysteresis v ov_hys 4 v serial interface (sda, scl, ad0, rst ) input high voltage v ih2 0.7 x v dd v input low voltage v il2 0.3 x v dd v input leakage current i in2 0.03 f a output low voltage sda v ol2 i sink = 6ma 0.3 v input capacitance c in2 10 pf
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 5 max6948b timing characteristics ( typical application circuit , v+ = 2.7v to 5.0v, v dd = 1.7v to v+, t a = t min to t max , unless otherwise noted. typical values are at v+ = 3.3v, v dd = 2.5v, t a = +25 n c.) (note 4) note 4: all parameters are tested at t a = +25 n c. specifications over temperature are guaranteed by design. note 5: the d i port_ specifies current matching between ports of a single part. note 6: current matching is defined as the percent error of any individual port from the average current of the maximum value measured and the minimum value measured. it can be found using the equation d i port_ = 100 x (i mmavg - i meas )/ i mmavg where i mmavg = (i measmax + i measmin )/2. note 7: guaranteed by design. note 8: a master device must provide a hold time of at least 300ns for the sda signal (referred to v il of the scl signal) to bridge the undefined region of scls falling edge. note 9: i sink p 6ma. c b = total capacitance of one bus line in pf. t r and t f are measured between 0.3 x v dd and 0.7 x v dd . note 10: input filters on the sda, scl, and ad0 inputs suppress noise spikes less than 50ns. parameter symbol conditions min typ max units internal boost-converter pwm clock frequency f int_ boost 98 125 145 khz internal gpio pwm clock frequency f int_gpio 24 31.25 38 khz scl serial-clock frequency f scl 400 khz bus free time between a stop and start condition t buf 1.3 f s hold time (repeated) start condition t hd, sta 0.6 f s repeated start condition setup time t su, sta 0.6 f s stop condition setup time t su, sto 0.6 f s data hold time t hd, dat (note 8) 0.9 f s data setup time t su, dat 180 ns scl clock low period t low 1.3 f s scl clock high period t high 0.7 f s rise time of both sda and scl signals, receiving t r (notes 7, 9) 20 + 0.1c b 300 ns fall time of both sda and scl signals, receiving t f (notes 7, 9) 20 + 0.1c b 300 ns fall time of sda transmitting t f, tx (notes 7, 9) 20 + 0.1c b 250 ns pulse width of spike suppressed t sp (notes 7, 10) 50 ns serial bus timeout t out 20 30 50 ms capacitive load for each bus line c b (note 7) 400 pf rst pulse width t w 1 f s
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 6 max6948b typical operating characteristics (v+ = 3.3v, v dd = 2.5v, t a = +25 n c, unless otherwise noted.) efficiency vs. v+ max6948b toc01 v+ (v) efficiency (%) 4.74 4.23 3.72 3.21 65 70 75 80 85 90 60 2.70 5.25 full-current 3 leds half-current 3 leds full-current 5 leds full-current 7 leds half-current 5 leds half-current 7 leds switching waveforms max6948b toc02 500mv/div v+ 5v/div v out 10v/div lx gnd soft-start v+, v out (10/1024) max6948b toc03 500mv/div v+ 5v/div v out soft-start v+, v out (512/1024) max6948b toc04 500mv/div v+ 5v/div v out soft-start v+, v out (1024/1024) max6948b toc05 500mv/div v+ 5v/div v out shutdown response (v+, v out) max6948b toc06 500mv/div v+ 5v/div v out gnd v+ (v) max6948b toc07 i wled (ma) 15 25 35 5 v+ (v) 4.54 4.08 3.62 3.16 2.70 5.00 i wled 30ma output current vs. v+ full-current 6 leds half-current 6 leds standby current i rst vs. v+ max6948b toc08 standby current ( a) 1 2 3 4 0 v+ (v) +85nc -40nc +25nc +105nc 4.54 4.08 3.62 3.16 2.70 5.00 5.3 5.4 5.5 5.6 5.7 5.8 5.2 max6948b toc09 standby current (ma) v+ (v) standby current i stby vs. v+ +25nc, +85nc, +105nc -40nc 4.54 4.08 3.62 3.16 2.70 5.00
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 7 max6948b typical operating characteristics (continued) (v+ = 3.3v, v dd = 2.5v, t a = +25 n c, unless otherwise noted.) 5.5 5.6 5.7 5.8 5.9 6.0 5.4 max6948b toc10 supply current (ma) v+ (v) supply current vs. v+ (boost on, 10% pwm, full current and half current) t a = -40nc, +25nc, +85nc, +105nc 4.54 4.08 3.62 3.16 2.70 5.00 supply current vs. v+ (boost on, 50% pwm, full current and half current) v+ (v) supply current (ma) 5.8 5.9 6.0 6.1 6.3 6.2 6.4 6.5 5.7 max6948b toc11 4.54 4.08 3.62 3.16 2.70 5.00 t a = -40 n c, +25 n c, +85 n c, +105 n c 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7.0 7.1 7.2 6.2 supply current vs. v+ (boost on, 10% pwm, full current and half current) max6948b toc12 t a = -40nc, +25nc, +85nc, +105nc v+ (v) supply current (ma) 4.54 4.08 3.62 3.16 2.70 5.00 delta supply current p2 vs. v+ (difference in current from port off to on) v+ (v) delta supply current p2 (ma) 5.35 5.40 5.45 5.50 5.60 5.55 5.65 5.70 5.30 max6948b toc14 4.54 4.08 3.62 3.16 2.70 5.00 +25 n c, +85 n c, +105 n c -40 n c output sinking current vs. v port max6948b toc15 v port (v) output sinking current (ma) 4 3 2 1 10 20 30 40 0 0 5 full-current po v+ = 5v half-current po full-current p2 half-current p2 output sinking current vs. v port max6948b toc16 v port (v) output sinking current (ma) 0.8 0.6 0.4 0.2 10 20 30 40 0 0 1.0 full-current po half-current po full-current p2 half-current p2 v+ = 5v stagger pwm port waveforms vs. time all (50% pwm) max6948b toc17 p0 p2 p3 p1 p4 boost 1ms/div delta supply current p0 vs. v+ (difference in current from port off to on) v+ (v) delta supply current p0 (ma) 5.35 5.40 5.45 5.50 5.60 5.55 5.65 5.70 5.30 max6948b toc13 4.54 4.08 3.62 3.16 2.70 5.00 +25 n c, +85 n c, +105 n c -40 n c
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 8 max6948b pin description pin configuration max6948b top view (bump in bottom) wlp (2.31mm x 2.31mm) a1 p0 p1 a2 a3 a4 a5 b1 b2 b3 b4 b5 scl sda v+ v dd ad0 v+ v+ p2 gnd n.c. i.c. comp p3 gnd fb pgnd pgnd p4 out ledsw lx lx rst c1 c2 c3 c4 c5 d1 d2 d3 d4 d5 e1 e2 e3 e4 e5 pin name function a1 p0 gpio port. open-drain i/o. p0 can be configured as a 30ma (max) constant sink current output. a2 rst active-low reset input a3 scl i 2 c-compatible, serial-clock input a4 sda i 2 c-compatible, serial-data i/o a5, b4, b5 v+ boost-converter supply voltage and positive supply voltage. bypass v+ to gnd with a 2.2 f f or higher value ceramic capacitor. b1 p1 gpio port. open-drain i/o. p1 can be configured as a 30ma (max) constant sink current output. b2 v dd i 2 c logic supply voltage. bypass v dd to gnd with a 0.1 f f or higher value ceramic capacitor. b3 ad0 address input. ad0 selects up to four device slave addresses (table 13). c1 p2 gpio port. open-drain i/o. p2 can be configured as a 10ma (max) constant sink current output. c2, d2 gnd ground. connect to pgnd. c3 n.c. no connection. internally not connected. c4 i.c. internally connected. connect i.c. to gnd for normal operation. c5 comp compensation terminal for the boost converter. a capacitor from comp to pgnd determines the boost-converter stability. d1 p3 gpio port. open-drain i/o. p3 can be configured as a 10ma maximum constant sink current output. d3 fb load current-sense voltage feedback for the boost converter. a resistor between fb and pgnd sets the maximum load current. d4, d5 pgnd power ground. connect pgnd to gnd. e1 p4 gpio port. open-drain i/o. p4 can be configured as a 10ma (max) constant sink current output. e2 out output voltage sense input for boost converter e3 ledsw high-voltage, constant-current input. connect ledsw to the cathode-end of the wled string. e4, e5 lx inductor switch node
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 9 max6948b detailed description the max6948b general-purpose input/output (gpio) peripheral with integrated boost converter provides a boost converter capable of driving 6 wleds and five i/o ports capable of driving leds powered from an alternate power supply such as the li+ battery. the integrated 2mhz boost converter minimizes the size and cost of external components and supplies 30ma of load current at up to 28v. the feedback input to the error amplifier has a typical set point of 0.1v to minimize power dis - sipation. external compensation keeps the converter stable under all load conditions from 5v up to 28v. the max6948b includes overvoltage and open-circuit detec - tion to prevent damage to the ic. an i 2 c-programmable 10-bit pwm signal enables 1024 levels of wled intensity. during pwm off-time, the internal switch at the ledsw pin disconnects the series wleds. this limits the pwm off-time leakage current to a minimum, limited only by the pwm switch internal to the max6948b. consequently, the boost output voltage remains almost constant during pwm on-/off-time peri - ods. this new approach provides advantages of minimal wled color change for sharp wled on and off, and more power efficiency due to minimal leakage. the five gpio ports function as logic inputs, open- drain logic outputs, or constant-current sinks in any combination. ports withstand 5.5v independent of the max6948bs supply voltage. two of the ports drive additional leds up to 30ma, while the other three ports drive leds at up to 10ma/port. the max6948b features shutdown and standby modes for low-power dissipa - tion. the constant-current drivers contain programmable pwm outputs and allow staggering to reduce the input peak current requirements. the i/o ports also feature ramp-up and ramp-down controls. the max6948b features a single input to select from four i 2 c slave addresses. programming and functionality for the five gpio ports is identical to the max6946/max6947 i/o expanders. functional block diagram sda scl ado thermal shutdown 125khz, 31.25khz oscillator bandgap reference current dac n-channel mosfet n-channel mosfet lx lx pgnd pgnd comp ledsw por v dd i 2 c interface control registers pwm and gpio logic led enable gpio enable gpio input port gpio and constant- current led drive ovp uvlo rst out v+ p0 fb p1 p2 p3 p4 max6948b pwm and gate drive
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 10 max6948b register description the max6948b contains 25 internal registers (table 1). registers 0x00 to 0x15 control ports p0Cp4 and remain compatible with the max6946/max6947 port expanders. register 0x20 and 0x21 set the pwm duty cycle for the integrated boost converter. register 0x22 conveys the boost-converter status. table 1. register address map and autoincrement address address code (hex) auto-increment address (hex) read/ write register function description 0x00 0x01 r/ w p0 port p0 i/o control and pwm settings 0x01 0x02 r/ w p1 port p1 i/o control and pwm settings 0x02 0x03 r/ w p2 port p2 i/o control and pwm settings 0x03 0x04 r/ w p3 port p3 i/o control and pwm settings 0x04 0x10 r/ w p4 port p4 i/o control and pwm settings 0x05 reserved 0x06 reserved 0x07 reserved 0x08 reserved 0x09 reserved 0x0a 0x10 r/ w group control (p0Cp4) write: simultaneously sets i/o and pwm settings for ports p0Cp4 read: reads contents of address 0x00 0x0b 0x10 r/ w group control (p0, p1) write: simultaneously sets i/o and pwm settings for ports p0, p1 read: reads contents of address 0x00 0x0c 0x10 r/ w group control (p2, p3, p4) write: simultaneously sets i/o and pwm settings for ports p2, p3, p4 read: reads contents of address 0x00 0x0d 0x10 reserved 0x0e 0x0e read only port input reads gpio input values 0x0f reserved 0x10 0x11 r/ w configuration half-/full-boost current, reset options, pwm stagger, start/stop status, reset run, shutdown setting 0x11 0x12 r/ w ramp-down port ramp-down and hold-off settings 0x12 0x13 r/ w ramp-up port ramp-up setting 0x13 0x14 r/ w output current port half-/full-current settings 0x14 reserved 0x15 0x10 r/ w global current port maximum current setting 0x20 0x21 r/ w boost pwm (msb) boost circuit led pwm setting (msb) 0x21 r/ w boost pwm (lsb) boost circuit led pwm setting (lsb) 0x22 r/ w boost status boost circuit status and standby setting
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 11 max6948b configuration register format (0x10) use the configuration register to select pwm phasing between outputs, monitor fade status, enable hardware startup from shutdown, and select shutdown or run mode (table 2). initial power-up on power-up, all control registers are set to power- up values and the max6948b is in shutdown mode (table 3). table 2. configuration register format (0x10) table 3. power-on reset (por) values register bit description value function default value d7 half-/full-boost current 1 half-boost current set by r fb 1 0 full-boost current set by r fb d6 reset/por option 0 rst does not change register data 0 1 rst resets registers to por values d5 pwm stagger 0 pwm outputs are in phase 0 1 pwm outputs are staggered d4 hold-off status 0 device is not in hold-off read only 1 device is in hold-off d3 ramp-down (fade-off) status 0 device is not in fade-off read only 1 device is in fade-off d2 ramp-up status 0 device is not in ramp-up read only 1 device is in ramp-up d1 reset-run enable 0 reset run disabled 0 1 reset run enabled d0 run 0 shutdown mode 0 1 run mode address code (hex) read/ write power-up value (hex) register function por description 0x00 r/ w 0xff p0 port p0 high impedance 0x01 r/ w 0xff p1 port p1 high impedance 0x02 r/ w 0xff p2 port p2 high impedance 0x03 r/ w 0xff p3 port p3 high impedance 0x04 r/ w 0xff p4 port p4 high impedance 0x10 r/ w 0x00 configuration shutdown mode (reset run disabled) 0x11 r/ w 0x00 ramp-down port ramp-down and hold-off disabled 0x12 r/ w 0x00 ramp-up port ramp-up disabled 0x13 r/ w 0x03 output current p0, p1 at full current; p2, p3, p4 at half current 0x15 r/ w 0x07 global current maximum output current 0x20 r/ w 0x00 boost pwm (msb) zero pwm duty cycle 0x21 r/ w 0x00 boost pwm (lsb) zero pwm duty cycle 0x22 r/ w 0x01 boost status boost circuit in standby mode
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 12 max6948b boost converter boost-converter output pwm the max6948b boost converter has 10-bit pwm opera - tion using an internal 125khz clock. this yields a pwm period of 1024/125k = 8.192ms. pwm operation allows the user to adjust the led intensity and lower the average current by enabling and disabling the boost converter at a selectable rate. this rate is set using the boost-con - verter output pwm registers (tables 4, 5). the duty cycle ranges from 0/1024 (no intensity or off) to 1023/1024 (full intensity). eight of the 10 bits, which include the msb, are in a single register (0x20) to allow a single i 2 c write to set the majority of the intensity level and minimize visible flicker during intensity changes. the lsb register (0x21) allows for very fine adjustments in led intensity. boost-converter status register the max6948b checks the boost converter and indi - cates its status in the boost-converter status register (table 6). faults indicated in this register include ther - mal shutdown, overvoltage, and current limit. the boost converter goes into standby mode whenever the boost standby bit (d0) = 1. table 4. boost-converter output pwm (msb) register format (0x20) table 5. boost-converter output pwm (lsb) register format (0x21) table 6. boost-converter status register format (0x22) x = dont care. register bit description value function default value d7 bit 9 boost-converter output pwm bit 9 (msb) 0 d6 bit 8 boost-converter output pwm bit 8 0 d5 bit 7 boost-converter output pwm bit 7 0 d4 bit 6 boost-converter output pwm bit 6 0 d3 bit 5 boost-converter output pwm bit 5 0 d2 bit 4 boost-converter output pwm bit 4 0 d1 bit 3 boost-converter output pwm bit 3 0 d0 bit 2 boost-converter output pwm bit 2 0 register bit description value function default value d7Cd2 reserved 000000 000000 d1 bit 1 boost-converter output pwm bit 1 0 d0 bit 0 boost-converter output pwm bit 0 (lsb) 0 register bit description value function default value d7, d6, d5 reserved 000 000 d4 schottky open 0 schottky diode present read only 1 schottky diode open d3 current limit 0 normal output current read only 1 converter output current exceeded the current limit d2 thermal shutdown 0 normal operation read only 1 device temperature has exceeded thermal shutdown threshold d1 overvoltage 0 normal operation read only 1 v out exceeded overvoltage limit d0 boost standby 0 boost converter operating according to pwm register and configuration register 1 1 boost converter in standby mode
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 13 max6948b boost-converter shutdown/standby modes the boost converter shuts down when d0 of the con - figuration register (0x10) = 0, or when d0 of the boost- converter status register (0x22) = 1. if both the boost pwm output registers (0x20, 0x21) values are zero, the boost converter remains in a low-current state (standby). undervoltage lockout (uvlo) undervoltage lockout (uvlo) disables the boost con - verter when v+ is below 2.4v (max). this resets bit d0 of the configuration register and puts the part into shut - down mode (0x10). quick start the max6948b quick starts by charging c comp with a current source. during this time, the internal mosfet is switching at the minimum duty cycle. once v comp rises above 0.2v, the duty cycle increases until the output voltage reaches the desired regulation level. in shutdown mode, comp is pulled to gnd with a 20k i internal resistor. overvoltage protection if the voltage on the output terminal rises above 28.5v (min), the converter is put into standby mode. this pro - tects the converter from excessive voltage in the event of an open-circuit condition. to detect if the boost con - verter has exceeded the overvoltage limit, read bit d1 of the boost-converter status register (0x22). once the output voltage has dropped 4v below the overvoltage threshold, the read-only bit (d1) goes to zero. the boost converter leaves standby mode and normal operation resumes. reading the register causes the bit to reset. if the fault is still active, the bit will be set again. thermal shutdown thermal shutdown limits total power dissipation in the max6948b. when the junction temperature exceeds 151 n c (typ), the boost converter and ports p0Cp4 turn off, allowing the part to cool. the thermal shutdown bit (d2) of the boost configuration and status register (0x22) is set high. bit d0 of the boost-converter status register (0x22) = 1, bit d0 of the configuration register (0x10) = 0 (reset), and the device is in shutdown mode. the max6948b turns on and begins to quick-start after the junction temperature cools by 10 n c. reading this regis - ter causes the bit to reset. if the fault is still active, the bit will be set again. current limit the max6948b current-limit function monitors the induc - tor current when the internal switch on the lx node is on. the device compares the inductor current to a fixed threshold. when the current exceeds the threshold, bit d3 of the boost-converter status register asserts and the switch shuts off for that cycle. reading this register causes the bit to reset. if the fault is still active, the bit will be set again. boost-converter current settings the boost current, through the serial output leds, can be set to half or full scale by setting the fb pin voltage. the fb voltage is set through bit d7 of the configuration register (0x10) (table 2). the fb voltage settings are 100mv or 200mv for half- or full-current mode operation, respectively.
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 14 max6948b i/o ports (p0Cp4) the max6948b contains five i/o ports (p0Cp4). configure the five i/o ports as logic inputs, open-drain logic outputs, or constant-current sinks in any combination. table 7 provides a detailed description of the individual port con - figuration registers. use registers 0x00 to 0x04 to individu - ally assign each port (see the pwm intensity control and phasing section). use registers 0x0a, 0x0b, and 0x0c to assign the same port setting to multiple ports (table 1). when powered off, the i/o ports remain in high impedance. figure 1 shows the i/o port structure of the max6948b. i/o ports p0Cp4 default to high impedance on power-up, to prevent connected ports from drawing current. ports used as inputs do not load their source signals. table 7. port registers format (0x00 to 0x04, 0x0a, 0x0b, and 0x0c) figure 1. simplified schematic of i/o ports register description register data d7 d6 d5 d4 d3 d2 d1 d0 port is logic-low. port is still active in shutdown mode. 0 0 0 0 0 0 0 0 port is logic-high. set this mode when using gpio as an input. port is still active when in shutdown mode. 0 0 0 0 0 0 0 1 port is a static constant-current sink. port is high impedance when in shutdown mode. 0 0 0 0 0 0 1 0 port is a constant-current sink with a 3/256 duty cycle. port is high impedance when in shutdown mode. 0 0 0 0 0 0 1 1 port is a constant-current sink with a 4/256 duty cycle. port is high impedance when in shutdown mode. 0 0 0 0 0 1 0 0 port is a constant-current sink with a 5/256 duty cycle. port is high impedance when in shutdown mode. 0 0 0 0 0 1 0 1 u u u port is a constant-current sink with a 254/256 duty cycle. port is high impedance when in shutdown mode. 1 1 1 1 1 1 1 0 power-up default setting (port is high impedance) 1 1 1 1 1 1 1 1 8-bit latch output port register pwm generator 1-bit latch output-current register 4-bit dac 3-bit latch global-current register read i/o port command to/from serial interface msb enable a b n-channel mosfet i/o port enable = 0x00 set current position a: 0x00 to 0x01 position b: 0x02 to 0xff close switch: 0x02 to 0xfe
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 15 max6948b ports configured as outputs the global-current register sets the full (maximum) constant-current sink amount for i/o ports configured as an output (table 8). power-up sets the global current to its maximum value. set each output ports individual constant-current sink to either half scale or full scale of the global current. use the output-current registers to set the individual currents (table 9). by default, p0 and p1 start up set to full cur - rent, while p2, p3, and p4 are set to half current. set each output current individually to best suit the maximum operating current of an led load, or adjust as needed to double the effective intensity control range of each output. the maximum individual current selection is 15ma (half) or 30ma (full) for ports p0 and p1, and 5ma (half) or 10ma (full) for ports p2, p3, and p4. table 8. global-current register format (0x15) x = dont care. table 9. output-current register format (0x13) register description register data d7 d6 d5 d4 d3 d2 d1 d0 reserved global current 3.75ma full-current value (p0, p1) 1.25ma full-current value (p2, p3, p4) x x x x x 0 0 0 7.5ma full-current value (p0, p1) 2.5ma full-current value (p2, p3, p4) x x x x x 0 0 1 11.25ma full-current value (p0, p1) 3.75ma full-current value (p2, p3, p4) x x x x x 0 1 0 15ma full-current value (p0, p1) 5ma full-current value (p2, p3, p4) x x x x x 0 1 1 18.75ma full-current value (p0, p1) 6.25ma full-current value (p2, p3, p4) x x x x x 1 0 0 22.5ma full-current value (p0, p1) 7.5ma full-current value (p2, p3, p4) x x x x x 1 0 1 26.25ma full-current value (p0, p1) 8.75ma full-current value (p2, p3, p4) x x x x x 1 1 0 30ma full-current value (p0, p1) 10ma full-current value (p2, p3, p4) x x x x x 1 1 1 power-up default 0 0 0 0 0 1 1 1 register bit description value function default value d7, d6, d5 reserved 0 0 d4 p4 0 port p4 is set to half current 0 1 port p4 is set to full current d3 p3 0 port p3 is set to half current 0 1 port p3 is set to full current d2 p2 0 port p2 is set to half current 0 1 port p2 is set to full current d1 p1 0 port p1 is set to half current 1 1 port p1 is set to full current d0 p0 0 port p0 is set to half current 1 1 port p0 is set to full current
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 16 max6948b pwm intensity control and phasing the max6948b uses an internal 31.25khz oscillator to generate pwm timing for led intensity control. a pwm period comprises 256 cycles of the nominal 31.25khz pwm clock (figure 2). each port can have an individual pwm duty cycle between 3/256 and 254/256. see table 7 for port register settings. configure pwm timing by setting the stagger bit in the configuration register (table 2), either with output stag - gering or without. set pwm stagger = 0 to cause all outputs using pwm to switch at the same time using the timing shown in figure 2. all outputs, therefore, draw load current at the exact same time for the same pwm setting. this means that if, for example, all outputs are set to 0x80 (128/256 duty cycle), the current draw would be zero (all loads off) for half the time, and full (all loads on) for the other half. set pwm stagger = 1 to stagger the pwm timing of the five port outputs and the integrated boost-converter out - put, distributing the port output switching points across the pwm period (figure 3). staggering reduces the di/dt output-switching transient on the supply and reduces the peak/mean current requirement. change the pwm stagger-setting bit during shutdown. changing the stagger bit during normal operation can cause a transient flicker in any pwm-controlled led because of the fundamental pwm timing changes. figure 2. static and pwm constant-current waveforms high-z low high-z low high-z low output low 254/256 duty constant current with input buffer disabled (pwm led drive) high-z low 0xff high-z low high-z low output low 253/256 duty constant current with input buffer disabled (pwm led drive) output static-high logic drive with input buffer enabled (gpi) output static-low logic drive with input buffer enabled (gpi) output static-low constant current with input buffer disabled (static led drive on) 0xfd 0xfe 0x02 0x00 0x01 output static high impedance with input buffer disabled (static led drive off) high-z low output low 3/256 duty constant current with input buffer disabled (pwm led drive) 0x03 high-z low output low 252/256 duty constant current with input buffer disabled (pwm led drive) 0xfc register value output 7.8125ms nominal pwm period high-z low output low 4/256 duty constant current with input buffer disabled (pwm led drive) 0x04
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 17 max6948b figure 3. staggered port and boost pwm waveform ports configured as inputs configure a port as a logic input by writing 0x01 to the ports output register (table 7). reading an input port register returns the logic levels from the i/o ports config - ured as a logic input (table 10). the input port register returns logic 0 in the appropriate bit position for a port not configured as a logic input. the input ports registers are read only. the max6948b ignores writes to the input ports register. standby mode and operating current configuring all the ports as logic inputs or outputs (all output registers set to value 0x00 or 0x01) or high imped - ance (output register set to value 0xff) puts the device into standby mode. put the max6948b into standby mode for lowest supply current consumption. setting a port as a constant-current output increases the operating current (output register set to a value between 0x02 and 0xfe), even if a load is not applied to the port. the max6948b enables an internal current mirror to provide the accurate constant-current sink. enabling the internal current mirror increases the devices supply current. each output contains a gated mirror, which acti - vates only when required. in pwm mode, the current mirror turns on only for the duration of the outputs on-time. this means that the operating current varies as constant-current outputs are turned on and off through the serial interface, as well as by the pwm intensity control. table 10. input ports register format (0x0e, read only) 8.192ms nominal port pwm period port 0 or ports and boost in phase port 2 staggered pwm period port 3 staggered pwm period port 1 staggered pwm period port 4 staggered pwm period boost staggered pwm period 42 84 126 168 210 256 next port pwm period next port pwm period port 0 or ports and boost in phase port 2 staggered pwm period port 3 staggered pwm period port 1 staggered pwm period port 4 staggered pwm period boost staggered pwm period port 0 or ports and boost in phase port 2 staggered pwm period register bit description value function d7, d6, d5 reserved 0 d4 p4 0 port p4 is logic input low, or is not set as an input 1 port p4 is logic input high d3 p3 0 port p3 is logic input low, or is not set as an input 1 port p3 is logic input high d2 p2 0 port p2 is logic input low, or is not set as an input 1 port p2 is logic input high d1 p1 0 port p1 is logic input low, or is not set as an input 1 port p1 is logic input high d0 p0 0 port p0 is logic input low, or is not set as an input 1 port p0 is logic input high
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 18 max6948b shutdown mode in shutdown mode, all ports configured as constant- current outputs (output register set to a value between 0x02 and 0xfe) switch off and become high impedance. shutdown does not affect ports configured as logic inputs or outputs (output registers set to value 0x00 or 0x01) (table 7). this means that any ports used for gpios are still operational in shutdown mode. put the max6948b into shutdown mode by setting the run bit (d0) = 0 in the configuration register (0x10) (table 2). exit shutdown by setting the run bit high through the serial interface or by using the reset-run option (see the reset-run option section). configure and control the max6948b normally through the serial interface in shut - down mode. all registers are accessible in shutdown mode. entering and/or exiting shutdown mode does not change any register values. changing a port from static logic-low (0x00) or static logic-high (0x01) to a constant-current value (0x02 to 0xfe) in shutdown mode turns that output off (logic-high or high impedance) like any other constant-current out - puts in shutdown. the new constant-current output starts just like any other constant-current outputs when exiting shutdown. changing a port from a constant-current value (0x02 to 0xfe) to static logic-low (0x00) or static logic-high (0x01) in shutdown causes that output to set to the value as a gpio output. the new gpio output is unaffected just like any other gpio output when exiting shutdown. ramp-up and ramp-down controls the max6948b provides controls that allow the output currents to ramp down into shutdown (ramp-down) and ramp up again out of shutdown (ramp-down) (figures 4, 5). ramp-down comprises a programmable hold-off delay that maintains the outputs at full current for a time before the programmed ramp-down time. after the hold- off delay, the output currents ramp down. the ramp-down register sets the hold-off and ramp-down times and allows disabling of hold-off and ramp-down (zero delay), if desired (table 11). the ramp-up register sets the ramp-up time and allows disabling of ramp-up (zero delay), if desired (table 12). the configuration register contains three status bits that identify the condi - tion of the max6948b, hold-off, ramp-down, or ramp-up (table 2). the configuration register also enables or dis - ables ramp-up. one write command to the configuration register puts the device into shutdown (using hold-off and ramp-down settings in the ramp-down register) and one read command to the configuration register deter - mines whether the reset run is enabled for restart, and whether the max6948b is currently in ramp-up or ramp- down mode. reset run needs to be used with ramp-up for it to work properly. ramp-up and ramp-down use the pwm clock for tim - ing. the internal oscillator always runs during a fade sequence, even if none of the ports uses pwm. the ramp-up and ramp-down circuit operates a 3-bit dac. the dac adjusts the internal current reference used to set the constant-current outputs in a similar manner to the global-current register (table 8). the max6948b scales the master-current reference to have all output constant-current and pwm settings adjust at the same ratio with respect to each other. this means the leds always fade at the same rate even if with different intensity settings. the boost circuit does not use the 3-bit dac. during ramp-down, the boost circuit remains at its programmed output until it shuts off completely at the end of the ramp-down period. the boost circuit turns on completely at the beginning of the ramp-up sequence. the maximum port output current set by the global-cur - rent register (table 8) also sets the point during ramp- down that the current starts falling, and the point during ramp-up that the current stops rising. figure 7 shows the ramp waveforms that occur with different global-current register settings.
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 19 max6948b figure 4. ramp-up behavior figure 5. hold-off and ramp-down behavior table 11. port ramp-down register format (0x11) exit shutdown command full current/ half current 0 1s 2s 1/4s 1/2s 1/8s 1/16s zero to 4s current ramp-up after cs run 4s zero to 4s hold-off delay before ramp-down zero to 4s current ramp-down after hold-off delay 1s 2s 4s 1s 2s 1/8s 1/16s 1/8s 1/16s zero to 8s current ramp-down 4s 1/4s 1/2s 1/4s 1/2s full current/ half current 0 register description register data d7 d6 d5 d4 d3 d2 d1 d0 reserved hold-off ramp-down immediately shuts down after hold-off delay x x x x x 0 0 0 0.0655s ramp-down from full current after hold-off delay x x x x x 0 0 1 0.131s ramp-down from full current after hold-off delay x x x x x 0 1 0 0.262s ramp-down from full current after hold-off delay x x x x x 0 1 1 0.524s ramp-down from full current after hold-off delay x x x x x 1 0 0 1.049s ramp-down from full current after hold-off delay x x x x x 1 0 1 2.097s ramp-down from full current after hold-off delay x x x x x 1 1 0
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 20 max6948b table 11. port ramp-down register format (0x11) (continued) x = dont care. table 12. port ramp-up register format (0x12) x = dont care. register description register data d7 d6 d5 d4 d3 d2 d1 d0 reserved hold-off ramp-down 4.164s ramp-down from full current after ramp-down delay x x x x x 1 1 1 zero ramp-down delay before fade-off x x 0 0 0 x x x 0.0655s ramp-down delay before fade-off x x 0 0 1 x x x 0.131s ramp-down delay before fade-off x x 0 1 0 x x x 0.262s ramp-down delay before fade-off x x 0 1 1 x x x 0.524s ramp-down delay before fade-off x x 1 0 0 x x x 1.049s ramp-down delay before fade-off x x 1 0 1 x x x 2.097s ramp-down delay before fade-off x x 1 1 0 x x x 4.164s ramp-down delay before fade-off x x 1 1 1 x x x power-up default 0 0 0 0 0 0 0 0 register description register data d7 d6 d5 d4 d3 d2 d1 d0 reserved ramp-up immediately starts up x x x x x 0 0 0 0.0655s ramp-up to full current x x x x x 0 0 1 0.131s ramp-up to full current x x x x x 0 1 0 0.262s ramp-up to full current x x x x x 0 1 1 0.524s ramp-up to full current x x x x x 1 0 0 1.049s ramp-up to full current x x x x x 1 0 1 2.097s ramp-up to full current x x x x x 1 1 0 4.164s ramp-up to full current x x x x x 1 1 1 power-up default 0 0 0 0 0 0 0 0
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 21 max6948b rst input the active-low rst input operates as a reset that voids any current i 2 c transaction involving the max6948b, forcing the device into the i 2 c stop condition. use the d6 bit in the configuration register (table 2) to configure rst to reset all the internal registers to the power-on- reset state (table 3). the rst input is overvoltage toler - ant to 5.5v. the max6948b ignores all i 2 c bus activity while rst remains low. the device uses this feature to minimize supply current in power-critical applications by effective - ly disconnecting the max6948b from the bus during idle periods. rst also operates as a bus multiplexer, allow - ing multiple devices to use the same i 2 c slave address. drive only one max6948b rst input high at any time to use rst as a bus multiplexer. the max6948b features a reset-run option. taking the rst input high brings the driver out of shutdown in addi - tion to its normal function of enabling the devices i 2 c interface. reset-run option the max6948b features a reset-run option enabling rst to bring the driver out of shutdown, in addition to its nor - mal function of enabling the max6948bs i 2 c interface. this provides an alternative method of bringing the driver out of shutdown to writing to the configuration register through the serial interface. the reset-run timing uses the internal pwm clock. after enabling the reset-run option, the max6948b uses the rising edge on rst , followed by no i 2 c interface activ - ity to the max6948b for 128 to 129 periods of the gpio pwm clock (32khz typ) to trigger the reset-run option. if this timeout period elapses without the max6948b acknowledging an i 2 c transaction, the device sets the run bit (d0) in the configuration register and brings itself out of shutdown, activating any programmed ramp-up. if rst pulses high for less than this timeout period to trigger a reset run, the max6948b ignores the pulse and continues to wait for a suitable trigger. cancel the reset-run trigger by transmitting an i 2 c com - munication to the max6948b before the timeout period elapses. the trigger cancels when the max6948b acknowledges the i 2 c transaction and requires send - ing at least the max6948bs i 2 c slave address. the minimum timeout period is equal to 4ms. the minimum i 2 c clock speed that guarantees a successful start bit and 8 data bits (9 bits total) within the minimum timeout period is 9/4ms equal to 2.25khz. canceling the reset- run trigger clears the reset-run bit (d1) in the configura - tion register, disabling reset run. the run bit (d0) in the configuration register remains cleared and the driver remains in shutdown. figure 6. output fade dac (global current = 0x07) figure 7. global current modifies ramp-down behavior 30ma 10ma 15ma 5ma 0ma p0, p1 current p2, p3, p4 current ramp-up full current 7/8 current 6/8 current 5/8 current 4/8 current 3/8 current 2/8 current 1/8 current zero current port current = half ramp-down port current = full 0ma 30ma 22.5ma 15ma 7.5ma 0ma p0, p1 current full current 7/8 current 6/8 current 5/8 current 4/8 current 3/8 current 2/8 current 1/8 current zero current 26.25ma 18.75ma 11.25ma 3.75ma 10ma 7.5ma 5ma 2.5ma 0ma p2, p3, p4 current 8.75ma 6.25ma 3.75ma 1.25ma ramp-up ramp-down global current = 0x07 global current = 0x06 global current = 0x05 global current = 0x04 global current = 0x03 global current = 0x02 global current = 0x01 global current = 0x00
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 22 max6948b figure 9. start and stop conditions figure 10. bit transfer serial interface figure 8 shows the 2-wire serial-interface timing details. serial addressing the max6948b operates as a slave that sends and receives data through an i 2 c-compatible 2-wire inter - face. the interface uses a serial-data line (sda) and a serial-clock line (scl) to achieve bidirectional com - munication between master(s) and slave(s). a master (typically a microcontroller) initiates all data transfers to and from the max6948b and generates the scl clock that synchronizes the data transfer. the max6948bs sda line operates as both an input and an open-drain output. a pullup resistor, typically 4.7k i , is required on sda. the max6948bs scl line operates only as an input. a pullup resistor is required on scl if there are multiple masters on the 2-wire interface, or if the master in a single-master system has an open-drain scl output. each transmission consists of a start condition (figure 9) sent by a master, followed by the max6948b 7-bit slave address plus r/ w bit, a register address byte, 1 or more data bytes, and finally a stop condition. start and stop conditions both scl and sda remain high when the interface is not busy. a master signals the beginning of a transmission with a start (s) condition by transitioning sda from high to low while scl is high. when the master has finished communicating with the slave, it issues a stop (p) con - dition by transitioning sda from low to high while scl is high. the bus is then free for another transmission. bit transfer one data bit is transferred during each clock pulse (figure 10). the data on sda must remain stable while scl is high. figure 8. 2-wire serial-interface timing details scl sda t r t f t buf start condition stop condition repeated start condition start condition t su, sto t hd, sta t su, sta t hd, dat t su, dat t low t high t hd , sta sda scl start condition stop condition s p sda scl data line stable; data valid change of data allowed
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 23 max6948b figure 11. acknowledge figure 12. slave address table 13. max6948b slave address map acknowledge the acknowledge bit is a clocked 9th bit (figure 11), which the recipient uses to handshake receipt of each byte of data. thus, each byte transferred effectively requires 9 bits. the master generates the 9th clock pulse, and the recipient pulls down sda during the acknowledge clock pulse, and therefore the sda line is stable-low during the high period of the clock pulse. when the master is transmitting to the max6948b, the max6948b generates the acknowledge bit because the max6948b is the recipient. when the max6948b is transmitting to the master, the master generates the acknowledge bit because the master is the recipient. slave addresses the max6948b has a 7-bit long slave address (figure 12). the bit following a 7-bit slave address is the r/ w bit, which is low for a write command and high for a read command. five bits (a6, a5, a4, a2, and a1), of the max6948b slave address are always 1, 0, 0, 0, and 0, respectively. slave address bits a7 and a3 correspond, by the matrix in table 13, to the states of the device address input ad0, and a0 corresponds to the r/ w bit. the ad0 input can be connected to any of four signals: gnd, v dd , sda, or scl, giving four possible slave-address pairs, allowing up to four max6948b devices to share the bus. because sda and scl are dynamic signals, care must be taken to ensure that ad0 transitions no sooner than the signals on sda and scl. the max6948b monitors the bus continuously, waiting for a start condition followed by its slave address. when the max6948b recognizes its slave address, it acknowl - edges and is then ready for continued communication. scl sda by transmitter clock pulse for acknowledge start condition sda by receiver 1 2 8 9 s sda a7 1 0 0 a3 0 0 r/w ack scl msb lsb pin ad0 device address a7 a6 a5 a4 a3 a2 a1 a0 gnd 0 1 0 0 0 0 0 r/ w v dd 0 1 0 0 1 0 0 r/ w scl 1 1 0 0 0 0 0 r/ w sda 1 1 0 0 1 0 0 r/ w
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 24 max6948b figure 13. command byte received figure 14. command and single data byte received figure 15. n data bytes received message format for writing the led driver a write to the max6948b comprises the transmission of the slave address with the r/ w bit set to zero, followed by at least 1 byte of information. the first byte of infor - mation is the command byte. the command byte deter - mines which register of the max6948b is to be written by the next byte, if received. if a stop condition is detected after the command byte is received, the max6948b takes no further action (figure 13) beyond storing the command byte. any bytes received after the command byte are data bytes. the first data byte goes into the internal regis - ter of the max6948b selected by the command byte (figure 14). if multiple data bytes are transmitted before a stop condition is detected, these bytes are generally stored in subsequent max6948b internal registers because the command-byte address generally autoincrements (table 1). message format for reading the max6948b is read using the max6948bs internally stored command byte as an address pointer, the same way the stored command byte is used as an address pointer for a write. the pointer generally autoincrements after each data byte is read using the same rules as for a write (table 1). thus, a read is initiated by first config - uring the max6948bs command byte by performing a write (figure 13). the master can now read n consecu - tive bytes from the max6948b, with the first data byte being read from the register addressed by the initialized command byte. when performing read-after-write verifi - cation, remember to reset the command bytes address because the stored command-byte address is generally autoincremented after the write (figure 15, table 1). s a a p 0 slave address command byte acknowledge from max6948b d15 d14 d13 d12 d11 d10 d9 d8 command byte is stored on receipt of stop condition acknowledge from max6948b r/w s a a a p 0 slave address command byte data byte 1 byte autoincrement memory address d15 d14 d13 d12 d11 d10 d9 d8 d1 d0 d3 d2 d5 d4 d7 d6 acknowledge from max6948b acknowledge from max6948b acknowledge from max6948b how command byte and data byte map into max6948b registers r/w s a a a p 0 slave address command byte data byte n bytes d15 d14 d13 d12 d11 d10 d9 d8 d1 d0 d3 d2 d5 d4 d7 d6 acknowledge from max6948b acknowledge from max6948b acknowledge from max6948b how command byte and data byte map into max6948b registers r/w autoincrement memory address
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 25 max6948b table 14. recommended inductors operation with multiple masters when the max6948b is operated on a 2-wire interface with multiple masters, a master reading the max6948b uses a repeated start between the write that sets the max6948bs address pointer, and the read(s) that takes the data from the location(s). this is because it is pos - sible for master 2 to take over the bus after master 1 has set up the max6948bs address pointer but before mas - ter 1 has read the data. if master 2 subsequently resets the max6948bs address pointer, master 1s read can be from an unexpected location. command address autoincrementing address autoincrementing allows the max6948b to be configured with fewer transmissions by minimizing the number of times the command address needs to be sent. the command address stored in the max6948b generally increments after each data byte is written or read (table 1). autoincrement only works when doing a burst read or write. applications information inductor selection the max6948b is optimized for a 10 f h inductor, although larger or smaller inductors can be used. using a smaller inductor results in discontinuous-current-mode operation over a larger range of output power, whereas use of a larger inductor results in continuous conduction for most of the operating range. to prevent core saturation, ensure that the inductors saturation current rating exceeds the peak inductor cur - rent for the application. for larger inductor values and continuous conduction operation, calculate the worst- case peak inductor current with the following formula: out out(max) in(min) peak in(max) v i v 0.5 s i 0.9 v 2 l = + otherwise, for small values of l in discontinuous conduc - tion operation, i peak is 860ma (typ). table 14 provides a list of recommended inductors. capacitor selection the typical input capacitor value is 2.2 f f and the typical output capacitor is 0.22 f f. higher value capacitors can reduce input and output ripple, but at the expense of size and higher cost. for best operation, use ceramic x5r or x7r dielectric capacitors. generally, ceramic capacitors with smaller case sizes have poorer dc bias character - istics than larger case sizes for a certain capacitance value. select the capacitor that yields the best trade-off between case size and dc bias characteristics. diode selection the high switching frequency of the max6948b demands a high-speed rectification diode for optimum efficiency. a schottky diode is recommended due to its fast recov - ery time and low forward-voltage drop. ensure that the diodes average and peak current rating exceeds the average output current and peak inductor current. in addition, the diodes reverse-breakdown voltage must exceed v out . compensation network selection the step-up converter uses an external compensation network from comp to gnd to ensure stability. for 5 or 6 wleds, choose c comp = c out /10 for optimal transient response. port input and i 2 c interface logic voltages the max6948b i 2 c supply (v dd ) accepts voltages from 1.7v up to the boost-converter input (v+). v dd determines the i 2 c interface (sda, scl), i 2 c slave- address select input (ad0), and reset input ( rst ) logic voltages. the five i/o ports p0Cp4 are overvoltage pro - tected to 5.5v independent of v dd or v+. this allows the max6948b to operate from one supply voltage, such as 3.3v, while driving some of the five i/os as inputs from a different logic level, such as 5v. vendor part number l (h) dcr (m ) i sat (a) case size (mm) toko 1069as-220m 22 570 0.47 3 x 3 x 1.8 toko 1098as-100m 10 290 0.75 2.8 x 3 x 1.2
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 26 max6948b figure 16. led brownout driving leds into brownout the max6948b correctly regulates the constant-current outputs, provided there is a minimum voltage drop across the port output. this port output voltage is the dif - ference between the load (typically led) supply and the load voltage drop (led forward voltage). if the led sup - ply drops so that the minimum port output voltage is not maintained, the driver output stages brownout and the load current falls. the minimum port voltage is approxi - mately 0.25v at 15ma sink current and approximately 0.3v at 30ma sink current (ports p0, p1) and 0.39v at 5ma sink current and approximately 0.4v at 10ma sink current (ports p2, p3, p4). operating the leds directly from a battery supply can cause brownouts. for example, the led supply voltage is a single rechargeable lithium-ion battery with a maxi - mum terminal voltage of 4.2v on charge, 3.4v to 3.7v most of the time, and down to 3v when discharged. in this scenario, the led supply falls significantly below the brownout point when the battery is at end-of-life voltage (3v). figure 16 shows the typical current sink by a king bright aa3020arwc/a white led as the led supply voltage is varied from 2.5v to 5.5v. the led currents shown are for ports programmed for 10ma and 30ma constant current, swept over a 2.5v to 5.5v led supply voltage range. it can be seen that the led forward voltage falls with current, allowing the led current to fall gracefully, not abruptly, in brownout. in practice, the led current drops to 11ma to 12.5ma at a 3v led supply voltage; this is acceptable performance at end-of-life in many backlight applications. output-level translation the open-drain output architecture allows the ports to level translate the outputs to higher or lower voltages than the max6948b supply (v dd ). use an external pullup resistor on any output to convert the high-impedance, logic-high condi - tion to a positive voltage level. connect the resistor to any voltage up to 5.5v. when using a pullup on a constant-cur - rent output, select the resistor value to sink no more than a few hundred f a in logic-low condition. this ensures that the current-sink output saturates close to gnd. for interfacing cmos inputs, a pullup resistor value of 220k i is a good starting point. use a lower resistance to improve noise immunity in applications where power consumption is less critical, or where a faster rise time is needed for a given capacitive load. using stagger with fewer ports the stagger option, when selected, applies to all ports configured as constant-current outputs. the pwm cycles are separated to six evenly spaced start positions (figure 3). optimize phasing when using some of the ports as constant-current outputs by allocating the ports with the most appropriate start positions. in general, choose the ports that spread the pwm start positions as evenly as possible. this optimally spreads out the cur - rent demand from the ports load supply. generating a shutdown/run output 4.5 4.0 3.5 3.0 5 10 15 20 25 30 35 0 2.5 5.0 i led vs. v led supply v led supply (v) i led (ma) v led vs. v led supply v led supply (v) v led (v) 5.0 4.5 3.0 3.5 4.0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 2.5 2.5 5.5
high-efficiency pwm led driver with boost converter and five constant-current gpio ports 27 max6948b the max6948b can use an i/o port to automatically gen - erate a shutdown/run output. the shutdown/run output is active-low when the max6948b is in run mode, hold-off, ramp-down, or ramp-up, and goes high automatically when the device finally enters shutdown after ramp- down. programming the ports output register to value 0x02 puts the output into static constant-current mode (table 7). program the ports output current to half cur - rent (table 9) to minimize operating current. connect a 220k i pullup resistor to this port. in run mode, the output port goes low, approaching 0v, as the ports static constant current saturates trying to sink a higher current than the 220k i pullup resistor can source. in shutdown mode, the output goes high impedance together with any other constant-current outputs. this output remains low during ramp-up and ramp-down sequences because the current drawn by the 220k i pullup resistor is much smaller than the available output constant current, even at the lowest fade-current step. driving load currents higher than 30ma the max6948b can drive loads needing more than 30ma, like high-current white leds, by paralleling out - puts. for example, consider a white led that requires 90ma. drive this led using the ports p0Cp4 connected in parallel (shorted together). configure all of the five ports for full current (2 x 30ma + 3 x 10ma) to meet the 90ma requirement. control the five ports simultaneously with one write access using register 0x0c (table 1). note that because the output ports are current limiting, they do not need to switch simultaneously to ensure safe current sharing. power-supply considerations v+ operates with a 2.7v to 5.5v power-supply voltage. bypass v+ to gnd with a 2.2 f f or higher ceramic capacitor as close as possible to the device. v dd oper - ates with a 1.7v to v+ power-supply voltage. bypass v dd to gnd with a 0.1 f f or higher ceramic capacitor as close as possible to the device. pcb layout considerations due to fast switching waveforms and high-current paths, careful pcb layout is required. minimize trace lengths between the ic and the inductor, the diode, the input capacitor, and the output capacitor. minimize trace lengths between the input and output capacitors and the max6948b gnd terminal, and place input and output capacitor grounds as close together as pos - sible. use separate power-ground and analog-ground copper areas, and connect them together at the output- capacitor ground. keep traces short, direct, and wide. keep noisy traces, such as the lx node trace, away from sensitive analog circuitry. for improved thermal per - formance, maximize copper area of the lx and pgnd traces. refer to the max6948b ev kit data sheet for an example layout.
high-efficiency pwm led driver with boost converter and five constant-current gpio ports maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 28 maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. max6948b chip information process: bicmos package type package code document no. 25 wlp b9-7 w252d2+1 21-0453 package information for the latest package outline information and land pat - terns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suf - fix character, but the drawing pertains to the package regardless of rohs status.

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